Figure 3. Top Side of Test Board
The
TG-EFT was set to produce 100 Volt pulses (with a rise time of 2 ns and
a fall time of about 100 ns). This setting would produce a current
pulse into the signal path on the board of about one Ampere since a
50 Ohm series termination was used on the output of the TG-EFT, similar to that shown in Figure 4, and the rest of the signal path is also 50 Ohms.
Figure 4. 50 Ohm Series Termination Used With TG-EFT Pulse Generator
Figures 5 and 6 show the scope plots that resulted when the TG-EFT
generator was connected to the path that stayed on one side of
the board and the path that was routed on both sides respectively. For
the path that stayed on the same side of the board, the plot in Figure
5 shows a peak amplitude of about 2 mV, a very small value. The peak
amplitude of the plot in Figure 6 resulting from the path that passed
between the top and bottom of the board is about 270 mV, a much larger
signal. Note that the ringing frequency in Figure 6 is about 240
MHz, the same as the resonant frequency measured in the frequency domain on this board in the
June 2010 Technical Tidbit.
The main ringing frequency in Figure 5 is much slower and is of such a
low
amplitude, it may be present in Figure 6 as well but too small to be
seen at the 100 mV/div vertical scale. That low frequency is not
due to a resonance in the board as the frequency noted in Figure 6 is.
Figure 5. Measured Voltage Between Planes for Signal That Stays on the Same Side of the Board
(Vertical scale = 2 mV/div, Horizontal scale = 10 ns/div)
Figure 6. Measured Voltage Between Planes for Signal That Routes on Both Sides of the Board
(Vertical scale = 100 mV/div, Horizontal scale = 10 ns/div)
There are many scenarios
where an Ampere or more of current can be dumped into the power-ground
structure of a PCB. For example, a wide bus that changes from the top layer
to the bottom layer of a backplane can generate substantial currents in the planes if the bits change all at once
in the same direction. Modern busses can also be faster than the 2 ns rise
time of the current used for this experiment, likely making the problem
worse.
As a test for one of my clients, I once dumped almost 90 Amperes of
current with a 5 ns rise time from the output of an EFT generator into
the 3.3 Volt power plane of a PCB relative to the ground planes. No
errors in the operation of the board were observed, a very good design
and much better than our test board used here by two orders of
magnitude or more.
This is a
limiting case compared with most four layer PCBs (only four "bypass caps"), but the effect described could represent a
significant problem for passive backplanes and connecting boards which
may have capacitors widely spaced if any at all. Some time ago I
reviewed the layout of a passive four layer board that connected SCSI signals
between two parts of a system. The SCSI paths came in on the top layer
and exited on the bottom layer to another
connector. I had the person doing the layout add bypass capacitors in
the field of vias of the SCSI signals as they passed from the top layer
to the bottom layer to prevent the effect shown above.
Given the above data, one could propose a design rule for four layer boards where critical or noisy signals
(bus, clock, reset, or similar) must pass from the top signal layer to the bottom
signal layer of a four layer board: The vias for these signals should be
located near an existing or added bypass capacitor.
Summary:
The use of a four layer PCB model shows that significant signal
voltages can be developed between the planes of a four layer board
under some circumstances when signals are routed between the top and bottom layers. A resulting design rule could be to locate
vias of noisy or important signals near bypass capacitors on four layer PCBs.